Wofür werden nicht maskierbare Interrupts verwendet?

Typically, a CPU can be set to ignore normal interrupts (IRQs), and an "Interrupt Disable" or "Interrupt Mask" register or bit is provided for this purpose. This is desired because you usually do not want to be "interrupted again" while handling an IRQ.

An NMI is a non-reset interrupt that cannot be masked or ignored by the CPU - there is no disable or mask register.

Hardware that generates NMIs can often be told to not generate them, so they usually can be indirectly disabled. For example, on the 8-bit NES, the display chip will generate an NMI at the end of drawing a frame, but you can set a certain bit on a certain register to tell the display chip not to do that. Other hardware connected to the CPU's NMI pin can still cause an NMI.

x86 hardware typically uses NMIs to indicate fatal hardware errors from the chipset. Windows will halt immediately upon receiving one (example). You can't use the NMI for anything else on x86 hardware (EDIT: I might be wrong about that, read the link below), and it's possible to tell the chipset (or some chipsets) not to send NMIs by writing to a specific I/O port.

I think uncorrectable errors from ECC RAM can trigger this. Modern x86 CPUs provide a mechanism called "Machine Check Exceptions" that trigger on hardware related issues as well, so newer chipsets may be doing something different. Read this for some further insight.

One example of where an NMI is useful is in an embedded system. Consider the possibility of failure where an electrostatic discharge sent the processor off into the weeds, where it could be stuck in a loop.

If this loop occurs while regular interrupts are turned off, then there is nothing the system can do to recover from the error mode. Since the NMI is non-maskable, i.e. can never be disabled, a signal on the NMI can get the processor back into a working state. This signal could be from a watchdog timer, or a co-processor, or a human activated button

A reset line is similar to a NMI, except it is not an interrupt. It is impossible to resume the background task if the interrupt handler decides it is not really a failure occurring. A NMI interrupt handler has that option.

Consider cases like a thermal event, where steps need to be taken to prevent damage, or a power failure where one needs to back up data in non-volatile storage before the power completely goes. These are the kind of events where a NMI is often used.